1. Field of the Invention
The invention relates to cyclic pipeline analog to digital conversion and, in particular, to cyclic pipeline analog to digital converters with dual mode sample and hold circuits.
2. Description of the Related Art
Cyclic pipeline analog to digital converters (ADC) are important in high speed circuit design. However, it is difficult to design a small-area, high-speed, and precise analog to digital circuit, especially considering inherent errors of capacitors and resistors generated during processing. Generally, tolerance of capacitance error is about 0.1%. As a result, precision of analog to digital converters is limited within 10 bits.
In typical circuit architecture, single end signals are often used because of smaller area and lower power consumption. Single end signals, however, are more easily disturbed by noise. Thus, if a circuit architecture is more sensitive to noise, differential signals are often used to reduce influence of common noise. In cyclic pipeline analog to digital converters, signal sources typically generate single end signals. Single end inputs are thus often used in analog to digital converter design and performance thereof is often influenced by nonlinear errors. If a differential input is adopted, a single end to differential end circuit needs to be added to a front stage circuit. Even if a single end to differential end circuit is added, optimum performance cannot be achieved.
In cyclic pipeline analog to digital converters, input signals are often sampled by a sample and hold circuit to precisely receive input signals. There are mainly two architectures: charge-redistribution and flip-around. Charge-redistribution cyclic pipeline ADCs often use single end signals and flip-around cyclic pipeline ADCs often use differential signals.
FIG. 1A is a circuit diagram of a sample and hold circuit in a charge-redistribution cyclic pipeline ADC. In such a sample and hold circuit, signals are stored in sampling capacitors Cs when a sampling signal Φ1 is high and a holding signal Φ2 is low. At the next time, the charge stored in the sampling capacitors Cs is transferred to a hold capacitor Cf when sampling signal Φ1 is low and holding signal Φ2 is high. FIG. 1B is a circuit diagram of a sample and hold circuit in a flip-around cyclic pipeline ADC. In such a sample and hold circuit, signals are stored in sampling capacitors Cs when sampling signal Φ1 is high and holding signal Φ2 is low. At the next time, input terminals of the sampling capacitors Cs are connected to output terminals the differential operational amplifier when sampling signal Φ1 is low and holding signal Φ2 is high.
In a charge-redistribution scheme, since charges are transferred from the sampling capacitors Cs to the hold capacitors Cf, variation in input common range has only little side effect. Thus, the charge-redistribution scheme is suitable for applications with single end signals. Moreover, the sampling capacitors and the holding capacitors need to be the same. There is, however, error of 0.1% (corresponding to accuracy of 10 bit) in capacitor matching in CMOS technology. When errors in each stage accumulate, differential nonlinearity (DNL) is significant, resulting in significant integral nonlinearity (INL). Thus, performance of the analog to digital converter is significantly degraded.
In a flip-around scheme, the same capacitor is used to accomplish sampling and holding. Not only half noise (kT/C) is cut off but also errors in capacitor matching are diminished. This scheme, however, is suitable for applications with differential signals. If an input signal is a single end signal, variation in input common range leads to errors in output common range, making single end signal not suitable for this scheme, especially in high speed circuits.